3. ACON-C/CG, PCON-C/CG
CC-Link
33
PLC Output
Address (* “n” shows the head register address per each axis).
one word = 16 bits
RWw (n+0) b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Target
Position
(Slave Word)
RWw (n+1) b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Target
Position
(Host Word)
When the target position is shown using the negative figure, it is expressed using the complement of 2.
RWw (n+2) b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Positioning
Width
(Slave Word)
32,768
16,384
8,192
4,096
2,048
1,024
512
256
128
64
32
16
8
4
2
1
RWw (n+3) b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Positioning
Width
(Host Word)
524,288
262,144
131,072
65,536
RWw (n+4) b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Speed
32,768
16,384
8,192
4,096
2,048
1,024
512
256
128
64
32
16
8
4
2
1
RWw (n+5) b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Acceleration/
Deceleration
256
128
64
32
16
8
4
2
1
RWw (n+6) b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Pressing
Current
Limit Value
128
64
32
16
8
4
2
1
RWw (n+7) b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Control
signal
BKRL
RMOD
DIR
PUSH
JOG+
JOG-
JVEL
JISL
SON
RES
STP
HOME
DSTR
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